As shown in FIG. 9, a serial communication circuit disclosed in JP-2001-77800A includes a microcomputer 1 and an integrated circuit (IC) 2. The IC 2 has a receiving shift register 4, a processing circuit 5, a sending shift register 6, a counter circuit 7, a NOR gate 8, and a timer circuit 9.
The first bit of the serial clock signal SCLK output from the microcomputer 1 causes the timer circuit 9 to start to count. Then, the timer circuit 9 sends a clear signal to the counter circuit 7 at a predetermined time interval. The time interval is shorter than a transmission interval of a serial input data SIN and greater than a transmission time of the serial input data SIN. Thus, even when the counter circuit 7 stops to count due to a missing or extra pulse of the serial clock signal SCLK, the counter circuit 7 is cleared by the timer circuit 9 and the serial communication is returned to a normal state.
When an interrupt occurs in the microcomputer 1, the output timing of the serial clock signal SCLK may be delayed. In this case, the start timing of the timer circuit 9 is delayed accordingly. In contrast, data from the processing circuit is set into the shift register 6 at a constant time interval. As a result, the IC2 continues to output error data to the microcomputer 1.